1. Field of the Invention
The present invention relates to a coding method, a coding apparatus, a decoding method, and a decoding apparatus. More particularly, the invention relates to a coding method, a coding apparatus, a decoding method, and a decoding apparatus whereby, upon execution of ECC coding following RLL coding, the code constraints on RLL code sequences are not disturbed, additional bits that would degrade upon insertion the coding ratio of ECC parity sequences are not inserted, and both soft-decision decoding and hard-decision decoding are carried out easily on the decoding side.
2. Description of the Related Art
Numerous recording/reproduction devices and communication devices transmit input information sequences in code sequences in order to lower the error rate of digitally transmitted information.
FIG. 1 is a block diagram showing a configuration example of a recording and reproduction system 1.
As shown in FIG. 1, the recording and reproduction system 1 is constituted by a recording device 11 and a reproduction device 12. The recording device 11 is made up of a coding block 21 and a recording block 22. The reproduction device 12 is composed of a reproduction block 31, an A/D (analog/digital) conversion block 32, a code detection block 33, and a decoding block 34.
In FIG. 1, an information sequence (input information sequence) from the user's side is input to the coding block 21. The coding block 21 codes the input information sequence into a code sequence at a ratio of m/n, where “m” stands for information word length, “n” for code word length, and “m/n” for coding ratio. It is often the case with coding that a plurality of coding schemes such as encryption, error correction coding, and RLL (run-length-limited) coding are used in combination.
The code sequence is input to the recording block 22 that records the input sequence to a recording medium, not shown, using an optical pickup, a magnetic head or the like. The signal recorded to the recording medium is moved from there to the reproduction device 12.
The recorded signal coming from the recording device 11 is converted by the reproduction block 31 of the reproduction device 12 using an optical pickup, a magnetic head or the like, from the recording medium into an analog reproduced signal. An analog equalizer, not shown, is used to equalize the analog reproduced signal to a signal having target equalization characteristics, before the signal is converted by the A/D conversion block 32 into a digital received signal at predetermined time intervals. The A/D conversion block 32 includes a phase synchronization circuit, not shown.
The code detection block 33 converts the digital received signal into a detected code sequence or a posterior probability information sequence thereof. The detected code sequence or posterior probability information sequence is input to the decoding block 34 whereby the input sequence is decoded at a ratio of n/m into a detected information word that constitutes a detected information sequence.
If the equalization by the analog equalizer is considered insufficient, a digital equalizer may be interposed between the A/D conversion block 32 and the code detection block 33. In recent years, the practice of getting the code detection block 33 to use a soft-decision detector such as a Viterbi detector has become prevalent. Furthermore, if the decoding block 34 adopts an iterative decoding scheme, the code detection block 33 may be configured to utilize a posterior probability detector capable of soft-decision input and soft-decision output.
A variety of codes have been studied for use by the coding block 21 in FIG. 1. With storage systems, in particular, the RLL code and ECC (error correcting code) are often employed in combination.
The Reed-Solomon code has long been practiced as a representative ECC. With communication systems, low-density parity-check codes capable of high levels of error detection have also been put to practical use in recent years.
Of the RLL codes, those with their maximum number of consecutive 0-bits (i.e., maximum run length) limited to “k” and their minimum number of consecutive 0-bits (minimum run length) limited to “d” in a code sequence prior to NRZI modulation are generally referred to as (d, k) RLL codes. Incidentally, NRZI (non-return to zero on one) modulation is a modulation system whereby the polarity of a recorded or transmitted signal is inverted at 1's and kept unchanged at 0's.
A code in which the number of continuous transitions in a recorded or transmitted coded sequence is limited is called the MTR (maximum transition run) code. With the MTR code, the maximum number of consecutive 1-bits falls between 2 and a larger but finite number in the code sequence prior to NRZI modulation. The code of which the maximum number of consecutive 1-bits prior to NRZI modulation is limited to 1 is not generally called the MTR code since the code is the same as the minimum RLL code known for many years. The MTR code is disclosed illustratively in the U.S. Pat. No. 5,859,601, January 1999, by J. Moon and B. Brickner (called Patent Document 1 hereunder) and in IEEE Trans. Magn. 32, p. 3992, 1996, by J. Moon and B. Brickner (called Non-Patent Document 1 hereunder).
The above-cited Patent Document 1 and Non-Patent Document 1 discuss the possibility that if the maximum run is 8 or more, then the code MTR=2 can be structured to provide a coding ratio of 7/8.
Although the expression MTR was used in Non-Patent Document 1 for the first time, the codes with their maximum number of consecutive 1-bits limited prior to NRZI modulation had been known before (e.g., Nyquist constraint codes).
The major characteristic of the MTR code is this: that by limiting the maximum number of consecutive 1-bits to a small number, the code allows a detector trellis dealing with the received signal having undergone partial response equalization to remove or reduce code sequences whose squared Euclidean distance is appreciably short, thereby affording coding gain to the system in use.
Even where the maximum number of consecutive 1-bits in the code is limited, if that number is appreciably large, the coding gain involved is very small. For this reason, the codes with their maximum number of consecutive 1-bits limited to 2 through 4 to enhance coding gain are often called MTR codes. The performance of the MTR codes with their maximum number of consecutive 1-bits limited to 2 through 4 is illustratively disclosed in detail by E. Solijanin in “Application of Distance Enhancing Codes,” IEEE Trans. Magn., Vol. 37, No. 2. pp. 762-767, March 2001 (called Non-Patent Document 2 hereunder).
If the signal-to-noise ratio (SNR) of the received signal remains constant, then the MTR constraint is strong. That is, the smaller the maximum number of consecutive 1-bits, the larger the gain for the code detector in use. However, reinforcing the MTR constraint generally lowers the coding ratio that can be attained and degrades the SNR. Thus how strong the MTR constraint should preferably be on a given code is correlated to the signal transmission characteristics of the system in use.
Since the MTR code is a code with its maximum run length of 1-bits limited, that code may be considered a sort of RLL code in a wider sense. In practice, the MTR codes have their maximum run length of 0-bits subject to a constraint as well.
Where the RLL code and ECC are used in combination as mentioned above, there are two ways to make up the combination: RLL coding is carried out after ECC (after ECC parity bits are added), or ECC coding is performed after RLL coding. The latter arrangement has been studied extensively in recent years because it can achieve error correction without being adversely affected by error propagation due to RLL decoding. The result is frequently a larger coding gain than before.
FIG. 2 is a block diagram showing a composition example of the coding block 21 that carries out ECC coding after RLL coding.
In FIG. 2, the input information sequence is fed to an RLL coding section 51 for RLL coding at the ratio of m1/n1 then outputted to an ECC parity generation section 52 and a selection section 53. Here, m1 and n1 are a natural number each and m1 is smaller than n1.
The ECC parity generation section 52 generates and outputs ECC parity bits.
The selection section 53 selects successively an RLL code sequence output from the RLL coding section 51 and a parity sequence output from the ECC parity generation section 52, and outputs the selected sequence as a code sequence.
In the coding setup of FIG. 2, there is no constraint on the run length of the parity sequence. This generally leads to the problem of the code sequence being highly subject to deterioration in terms of the minimum run length constraint, MTR constraint, and maximum run length constraint.
A number of methods have been known for easing the problem of deterioration in terms of the MTR constraint and RLL resulting from parity insertion.
A first method involves interleaving the ECC parity sequence with the RLL code sequence before ECC coding in the coding setup of FIG. 2. That is, the parity sequence is periodically inserted into the RLL code sequence before ECC coding. This method is disclosed illustratively by J. L. Fan and J. M. Cioffi in “Constrained Coding Techniques for Soft Iterative Decoders,” Proc. IEEE (Globecom '99), pp. 723-727 (called Non-Patent Document 3 hereunder).
According to the method disclosed in Non-Patent Document 3, if the character α is assumed to represent the maximum run length of the RLL code sequence before parity insertion, then the maximum run length of the code sequence after parity insertion deteriorates down to α+ε, where ε stands for a natural number. If the coding ratio of ECC is larger than α/(α+ε), then the number ε may be the smallest natural number 1.
However, the method disclosed in Non-Patent Document 3 has one problem: where the RLL code sequence is subject to the minimum run length constraint and MTR constraint, the use of this method can degrade these constraints by at least one order of magnitude.
Generally, even if the maximum run length constraint on the RLL code sequence is degraded by one order of magnitude, it does not trigger appreciable deterioration in system performance. However, the minimum run length constraint or MTR constraint can significantly worsen system performance if degraded by one order of magnitude.
One way to bypass the above problem is to perform first RLL coding on the input information sequence and second RLL coding on the ECC parity sequence, before inserting a second RLL code sequence periodically into a first RLL code sequence. This method is disclosed by H. Song, R. M. Todd and J. R. Cruz in “Application of Low-density Parity-check Codes to Magnetic Recording Channels,” IEEE Trans. on Sel. Areas in Comm., Vol. 19, No. 5, pp. 918-923, May 2001 (called Non-Patent Document 4 hereunder).
FIG. 3 is a block diagram showing another composition example of the coding block 21 that performs second RLL coding on an ECC parity sequence.
In FIG. 3, those components also found in FIG. 2 are designated by like reference numerals. The structure in FIG. 3 differs from the structure in FIG. 2 in that an RLL coding section 54 performing second RLL coding on the ECC parity sequence is located downstream of the ECC parity generation section 52.
In FIG. 3, the input information sequence is fed to the RLL coding section 51 for first RLL coding at the ratio of m1/n1. The information sequence thus coded is input to the ECC parity generation section 52 and selection section 53.
The ECC parity generation section 52 generates and outputs parity bits. The parity sequence output from the ECC parity generation section 52 is forwarded to the RLL coding section 54 for second RLL coding at a ratio of m2/n2, where m2 and n2 are a natural number each and m2 is smaller than n2.
The selection section 53 selects periodically the sequence output from the RLL coding section 51 and the sequence from the RLL coding section 54. The selected sequence is output as a code sequence.
According to the method described in Non-Patent Document 4, a simple bit insertion technique is adopted to implement second RLL coding. This arrangement is intended to facilitate soft-decision decoding that may be used for ECC decoding on the decoding side. If a complicated technique were utilized in carrying out second RLL coding, then it would become necessary to perform complicated soft-decision decoding upon ECC decoding, which would require installing a complex decoding circuit.
The coding setup of FIG. 3 has the advantage of preventing the code constraint on the RLL code sequence before ECC coding from getting degraded after ECC coding. On the other hand, the total coding ratio can become worse than m1/n1 under the influence of the coding ratio of m2/n2 at the RLL coding section 54.
The above problem is circumvented by the technique of performing first RLL coding on the input information sequence and inserting the ECC parity sequence into the RLL code sequence before carrying out second RLL coding at the coding ratio of 1. This technique is disclosed illustratively by A. Hirano, S. Mita, and Y. Watanabe in “Coding Apparatus and Coding Method,” U.S. Pat. No. 6,335,841 B1, January 2002 (called Patent Document 2 hereunder).
FIG. 4 is a block diagram showing another composition example of the coding block 21 which is disclosed in the above-cited Patent Document 2 and which carries out second RLL coding at the coding ratio of 1 after inserting the ECC parity sequence into a first RLL code sequence.
In FIG. 4, those components also found in FIG. 2 are designated by like reference numerals. The structure in FIG. 4 differs from the structure in FIG. 2 in that an RLL coding section 55 is installed to perform second RLL coding at the coding ratio of 1 on the sequence output from the selection section 53.
In FIG. 4, the input information sequence is fed to the RLL coding section 51 for first RLL coding at the ratio of m/n. The RLL code sequence is output to the ECC parity generation section 52 and to the selection section 53.
The ECC parity generation section 52 generates and outputs ECC parity bits.
The selection section 53 periodically selects the RLL code sequence output from the RLL coding section 51 and the parity sequence output from the ECC parity generation section 52, and outputs the selected sequence.
The sequence output from the selection section 53 is forwarded to the RLL coding section 55 for second RLL coding at the coding ratio of 1. The RLL coding section 55 outputs the result of the coding as a code sequence.
In the structure described in the above-cited Patent Document 2, not all RLL coding is carried out by the RLL coding section 51 in FIG. 4; the RLL coding section 55 is used to accomplish the whole RLL coding desired. As an example of code conversion by the RLL coding section 55, if a sequence of [0001,1,1100] is given to represent the last 4 bits of the preceding first RLL code word, a parity 1-bit, and the first 4 bits of the current first RLL code word, then the sequence is converted to [0001,0,1110].